The present invention relates to an equalizing receiver; and, more particularly, to an equalizing receiver with data to clock skew compensation by compensating an inter-symbol interference (ISI) between signals.
The amount of data transmission as well as transmission rate of the data in communications between DRAM(dynamic random access memory) and CPU(central processing unit) or between digital chips such as ASIC (application specific integrated circuit) have been kept rising.
However, in such communications the data transmission rate is limited by a time jitter occurring in a PLL (phase locked loop)/DLL (delay locked loop) circuit, an offset due to dimensional deviations in the process of producing transmitters and receivers and so on. Also a setup/hold time of a receiver circuit is not sufficiently long enough, due to a reduction in a data size margin and a time margin resulting from an ISI between signals. In such a case the ISI is generated by attenuation in high frequency components of signals in a transmission channel. Moreover, a time skew is generated due to a difference, in time required for transmitting a signal through a channel, between signals or between clock and the signal.
Furthermore, in order to transmit a signal at a high speed by overcoming a bandwidth limitation generated in transmission channels of a bus structure where a plurality of chips are connected to one conductive line in a digital system, pre-emphasis is frequently employed as an equalizing technology adopted in a transmitter.
FIGS. 1A to 1C show a conventional principle of operating an equalizing circuit in the transmitter. A current method of technology for amplifying and transmitting a high frequency component of a signal inputted requires an additional current to the equalizing circuit during a signal variation.
Referring to FIG. 1B, when an output signal of a transmitter 10 in FIG. 1A is switched from an original low level to an original high level, an additional current is provided so that the signal is emphasized to a higher level than the original high level for one time period, and if there is no variation in an input signal fed to the transmitter 10 after the one time period, the signal is changed from the higher level to the original high level. When the output signal of the transmitter 10 is switched from the original high level to the original low level, an additional current is provided so that the signal is emphasized to a lower level than the original low level for one time period, and if there is no variation in the input signal fed to the transmitter 10 after the one time period, the signal is changed from the lower level to the original low level. Therefore, a receiver 12 in FIG. 1C can receive a signal that has been compensated for an attenuation in a high frequency component, occurring in a transmission channel.
However, the above-mentioned equalizing technology employed in the transmitter cannot be used in a system employing a full swing voltage method in controlling signals. In a system employing such method, emphasis on the output signal cannot be obtained due to a full swing of voltage in the transmitter. Thus, the ineffective equalizing technology employed in the transmitter becomes a bottleneck in a high speed transmission in case a bandwidth of a channel is limited. Examples of systems that employ the technology for controlling signal by the full swing voltage method in a transmitter are xe2x80x9cDDR (double data rate) SDRAMxe2x80x9d, xe2x80x9cSDR (single data rate) SDRAMxe2x80x9d, and the like.
Due to a difference in time required for transmitting a signal through a channel, there is a time skew between transmitted signals and between a clock and a transmitted signal. The skew has an adverse effect on a transmission at high speed. For the normal operation of an input circuit in a receiver, a setup/hold time should be sufficient as needed, but the skew makes it difficult.
As shown in FIG. 2, in the prior art, in order to determine a suitable timing of a clock, a proper sampling time is determined by over-sampling a transmitted signal (data are sampled twice or more per one period of a signal) per each data pin. That is, the data of the signal are sampled three times in two periods of the signal, and if first two samples have a same value, a delay of a sampling clock is increased. On the other hand, if last two samples have a same value, the delay time of the sampling clock is reduced. Through this feedback procedure, clock with a suitable delay (the timing of a sampling clock is determined to be in the middle of a specific portion of a stream of the data) is provided for a pin based on the difference in delay of the data.
In determining a suitable timing of a clock by the over-sampling method, a signal with minimal attenuation in time scale should be used. That is, if a high frequency component of the signal is considerably attenuated in the course while passing through a transmission channel, a time uncertain region of data shown in FIG. 2 is broadened, and the method for determining the suitability of the clock by the over-sampling becomes ineffective. Thus the method cannot be used in a channel where a high frequency component of a signal is seriously attenuated.
In transmitting a signal in the above-mentioned digital system, there are problems as follows.
First, when a signal is transmitted at a high speed in a channel of the digital system, a high frequency component in the signal may be attenuated. Such phenomenon causes an ISI between signals and reduces a time margin and a voltage margin of an input signal. Thus, there is great difficulty in achieving data transmission at a high speed.
Second, in the prior art, in order to solve such phenomenon, an equalizing technology is applied to a terminal of a transmitter, so that the attenuated component is compensated. However, such equalizing technology is not applicable to DRAM or ASIC where a voltage at the terminal of the transmitter has a waveform of a full swing.
Third, when a clock signal is transmitted with data from the transmitter to a receiver, a skew is generated due to a difference in a delay time which is a time required for the signal to pass through a transmission channel, which in turn reduces a time margin of data.
Fourth, in order to solve the skew problem, an oversampling technology is employed to find a suitable timing of clock. However, in the occurrence of an attenuation of a signal, there is great difficulty in applying such method to a broadened time uncertain region.
It is, therefore, an object of the present invention to provide an equalizing receiver for compensating an attenuation of a high frequency component in a signal and further over-sampling the compensated signal so that a skew between the data and clock is compensated, thereby facilitating a high speed data transmission.
In accordance with the present invention, there is provided an equalizing receiver performing on data to clock skew compensation, the equalizing receiver including: an equalizer for equalizing an external data signal fed thereto; an over-sampler for sampling the equalized data signal provided by the equalizer against a sampling clock; a clock-data phase detector for determining a timing of the sampling clock by analyzing an output of the over-sampler; and a clock synthesizer for providing the over-sampler with the sampling clock obtained by synthesizing an external clock signal based on the timing of the sampling clock, wherein the equalizer includes a first and a second equalizing amplifier and the over-sampler includes a first, a second, a third and a fourth sense amplifier, in which an output signal thereof is divided into an even and an odd branch.